Digital Signal Processor Product Preview

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PRODUCT PREVIEW
10
8
4
3
7
12
5
6
14
2
3
13
Stop Start Repeated
Start
Stop
SDA
SCL
1
11 9
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 7-42. I2C Receive Timings
Table 7-53. Switching Characteristics for I2C Timings
(1)
(see Figure 7-43 )
-720
-850
-1000
NO. PARAMETER UNIT
STANDARD MODE FAST MODE
MIN MAX MIN MAX
16 t
c(SCL)
Cycle time, SCL 10 2.5 µ s
Delay time, SCL high to SDA low (for a
17 t
d(SCLH-SDAL)
4.7 0.6 µ s
repeated START condition)
Delay time, SDA low to SCL low (for a START
18 t
d(SDAL-SCLL)
4 0.6 µ s
and a repeated START condition)
19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µ s
20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µ s
21 t
d(SDAV-SDLH)
Delay time, SDA valid to SCL high 250 100 ns
Valid time, SDA valid after SCL low (For I
2
C
22 t
v(SDLL-SDAV)
0 0 0.9 µ s
bus™ devices)
Pulse duration, SDA high between STOP and
23 t
w(SDAH)
4.7 1.3 µ s
START conditions
24 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(1)
300 ns
25 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(1)
300 ns
26 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(1)
300 ns
27 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(1)
300 ns
Delay time, SCL high to SDA high (for STOP
28 t
d(SCLH-SDAH)
4 0.6 µ s
condition)
29 C
p
Capacitance for each I2C pin 10 10 pF
(1) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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