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TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
7.7.3.4 PLL Controller Divider 4 Register
The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 .
Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the system.
Disabling this clock will cause unpredictable system behavior. Therefore, the PLLDIV4 register should
never be used to disable SYSCLK4.
31 16
Reserved
R-0
15 14 5 4 0
D4EN Reserved RATIO
R/W-1 R-0 R/W-3
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Figure 7-14. PLL Controller Divider 4 Register (PLLDIV4) [Hex Address: 029A 0160]
Table 7-22. PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
Bit Field Value Description
31:16 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15 D4EN Divider 4 enable bit.
0 Divider 4 is disabled. No clock output.
1 Divider 4 is enabled.
14:5 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0 RATIO 0-1Fh Divider ratio bits.
0 ÷2. Divide frequency by 2.
1h ÷4. Divide frequency by 4.
2h ÷6. Divide frequency by 6.
3h ÷8. Divide frequency by 8.
4h-7h ÷10 to ÷16. Divide frequency by 10 to divide frequency by 16.
8h-1Fh Reserved, do not use.
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