Computer Hardware User's Guide
Index
Index-16
timer-period register, definition D-7
timing
external interface
expansion bus I/O cycles 9-21–9-36
primary bus cycles 9-15–9-20
external memory interface 9-15–9-38
TMS320C30
architecture, block diagram 2-3
DMA controller 12-49
arbitration 12-63
external memory interface 9-1–9-38
interrupt vector table 7-26
memory maps 4-4
memory organization, block diagram 2-14
serial ports 12-15
timers 12-2
TMS320C31
architecture, block diagram 2-4
boot loader 11-2
DMA controller 12-49
arbitration 12-63
external memory interface 9-1–9-38
interrupt and trap memory maps 11-12
interrupt vector table 7-26
memory maps 4-5, 4-6
memory organization, block diagram 2-15
serial ports 12-15
timers 12-2
TMS320C32
architecture, block diagram 2-5
boot loader 11-14
data memory 2-20
data types and sizes 2-20
DMA controller 12-49
arbitration 12-63
external memory interface 2-19, 10-1–10-52
interrupt vector table 7-29
memory, external widths 2-20
memory organization, block diagram 2-16
program memory 2-19
serial ports 12-15
short floating-point format 5-4, 5-6
timers 12-2
trap vector locations 7-30
TMS320C3x
device differences 2-27
devices 1-2
compared 1-5
DSPs, introduction 1-1
functional block diagram 1-3
TMS320C3x (continued)
key specifications 1-3
serial port interface examples 12-41–12-48
TMS320LC31, power management mode, LOPOW-
ER 7-51–7-52
transfer-counter register 12-51
trap 7-11–7-12
conditionally instruction (TRAPcond) 7-11,
13-243
flow, block diagram 7-47
initialization 7-47
interrupt considerations, ’C30 7-44–7-46
operation 7-47
vector locations 3-15
traps 4-14
two parallel stores, instruction word format 8-29
U
unsigned-integer format 5-3
single-precision 5-3
V
variable data-rate timing operation 12-39
burst mode 12-35
continuous mode 12-40
W
wait state
definition D-8
generation 9-11
programmable 9-10–9-11, 10-15–10-16
wait-state generator, definition D-8
X
XF0, XF1 signals 2-21
Z
zero condition flag 13-29
zero fill, definition D-8
zero wait-state 9-15
zero-logic interconnect of devices 7-18
zero-overhead looping 7-2