Computer Hardware User's Guide

Index
Index-15
serial port (continued)
loading 11-11
memory mapped locations for 12-17
operation configurations 12-29–12-31
port control register
FSR/DR/CLKR 12-23–12-24
FSX/DX/CLKX 12-22–12-23
receive/transmit timer
control register 12-25–12-27
counter register 12-27
period register 12-28
registers 12-15, 12-47
timing 12-31–12-34
short
floating-point format, definition D-7
integer format 5-2
definition D-7
unsigned integer format, definition D-7
SIGI instruction 7-14
timing diagram for 7-15
signal, interlocked instruction (SIGI) 13-213
sign-extend, definition D-7
single-precision
floating-point format, definition D-7
integer format 5-2
definition D-7
unsigned integer format, definition D-7
software interrupt
definition D-7
instruction (SWI) 13-242
source-address register 12-51
stack 6-30–6-31
building 6-30
definition D-7
implementation of high-to-low memory 6-30
implementation of low-to-high memory 6-31
management 6-29–6-32
pointer 6-29
standard branch 7-9
example 8-5
status (ST) register 3-5, 13-29
CPU register file 3-5
definition D-7
global interrupt enable (GIE) bit
’C30 interrupt considerations 7-44
’C3x interrupt considerations 7-41
STFI instruction 7-14
STII instruction 7-14
store
floating-point value
(STF) 13-214
interlocked (STFI) 13-215
integer
instruction (STI) 13-219
interlocked (STII) 13-220
STRB signal 9-3, 9-15
STRB0
control register 10-8
STRB1
control register 10-8
subtract
floating-point value instruction (SUBF) 13-228
integer
(SUBI) 13-234
conditionally instruction (SUBC) 13-226
with borrow instruction (SUBB) 13-223
reverse
floating-point value instruction
(SUBRF) 13-240
integer
(SUBRI) 13-241
with borrow instruction (SUBRB) 13-239
synchronization, DMA channels 12-65
synchronize two processors, example 7-19
system management 6-29–6-32
system-stack pointer (SP) register 3-4, 6-29
T
test bit fields instruction (TSTB) 13-245
timer 2-23, 12-2–12-14
block diagram 12-2
control register 12-13
receive/transmit 12-25–12-27
counter 12-2
counter register 12-3, 12-7
receive/transmit 12-27
definition D-7
global-control register 12-3, 12-4–12-6
I/O port configurations 12-10
initialization/reconfiguration 12-13–12-17
interrupts 12-13
operation modes 12-10–12-12
output generation examples 12-9
period register 12-3, 12-7
receive/transmit 12-28
pulse generation 12-7–12-9
registers 12-47
timing figure 12-8