Computer Hardware User's Guide
Index
Index-12
peripherals 12-1–12-68
DMA controller 12-48–12-68
CPU/DMA interrupt enable regis-
ter 12-59–12-62
destination- and source-address regis-
ters 12-57–12-59
global-control register 12-53–12-59
Initialization/reconfiguration 12-73
memory transfer timing 12-67–12-68
programming examples 12-74–12-80
transfer-counter register 12-58–12-59
general architecture 2-22
serial ports 12-15–12-47
data-transmit register 12-28
data-receive register 12-28–12-29
FSR/DR/CLKR port control regis-
ter 12-23–12-24
FSX/DX/CLKX port control regis-
ter 12-22–12-23
functional operation 12-35–12-41
global-control register 12-17–12-21
initialization/reconfiguration 12-41
interrupt sources 12-34
operation configurations 12-29–12-31
receive/transmit timer control regis-
ter 12-25–12-27
receive/transmit timer counter register 12-27
receive/transmit timer period register 12-28
timing 12-31–12-34
TMS320C3x interface exam-
ples 12-41–12-48
timers 12-2–12-14
global-control register 12-4–12-6
initialization/reconfiguration 12-13–12-17
interrupts 12-13
operation modes 12-10–12-12
period and counter registers 12-7
pulse generation 12-7–12-9
pin operation, states at reset 7-21
pipeline
conflicts 8-4
branch 8-4
memory 8-8, 8-9
register 8-6
resolving (memory) 8-22
decode unit 8-2
definition D-6
execute unit 8-2
fetch unit 8-2
memory accesses 8-24
pipeline (continued)
operation 7-42
introduction 8-1
read unit 8-2
structure 8-2
major units 8-2
POP
floating-point value instruction (POPF) 13-195
integer instruction 13-194
power-management modes 7-49–7-52
IDLE2 7-49–7-51
primary bus 9-2
bus cycles 9-15–9-20
control register 9-7–9-8
bits described 9-7
BNKCMP and bank size 9-12, 10-17
full speed accesses 9-15
functional timing of operations 9-15
interface, signals 9-4
programmable
bank switching 9-13, 10-18
wait states 9-10–9-11, 10-15–10-16
program
buses 2-18
control, instructions 13-4–13-5
counter, definition D-6
fetch
incomplete 8-11
multicycle program memory fetches 8-12
flow control 7-1–7-52
calls, traps, and returns 7-11–7-12
delayed branches 7-9–7-10
interlocked operations 7-13–7-20
interrupt vector table,
TMS320C32 7-29–7-30
interrupts 7-26–7-37
control bits 7-32
CPU interrupt latency 7-35–7-36
CPU/DMA interaction 7-40
prioritization 7-31
processing 7-33–7-35
TMS320C30 considerations 7-44–7-47
TMS320C3x considerations 7-41–7-43
vector table 7-26–7-28
power-management mode 7-49–7-52
repeat modes 7-2–7-8
nested block repeats 7-8–7-15
RC register value after repeat mode 7-7
repeat-mode control bits 7-3
repeat-mode operation 7-3–7-4
restrictions 7-6–7-7