Computer Hardware User's Guide
Index
Index-6
data-rate timing operation
fixed 12-36
burst mode 12-36
continuous mode 12-36
variable 12-39
burst mode 12-35
continuous mode 12-40
data-page pointer (DP) 2-10, 3-4
data-receive register (DRR) 12-28
serial port 12-28–12-29
data-transfer operation, handshake 11-20
data-transmit register (DXR) 12-28, 12-32, 12-36,
12-37
data-address generation logic, definition D-2
data-page pointer (DP), definition D-2
DBR instruction 8-8
decode phase, definition D-3
decrement and branch
conditionally
delayed instruction (DBcondD) 13-97
standard instruction (DBcond) 13-95
instruction (DBR) 8-8
delayed branch 7-9–7-10
correct device operation 7-50
example 8-6
incorrectly placed 7-7
dequeue (stacks) 6-29, 6-31
destination-address register 12-51
direct addressing 6-4–6-29
direct memory access (DMA) 2-24
disabled interrupts by branch 7-9
displacements
indirect addressing 6-5
PC-relative addressing 6-19
divide clock by 16 instruction (LOPOWER) 13-135
DMA
architecture 2-24
block moves 12-48
buses 2-18
controller 2-18, 2-24, 12-48–12-68
2-channel, TMS320C32 12-49
address generation 12-57
arbitration 12-63
basic configuration 12-51
basic operation 12-50
block diagram 2-25
channel synchronization 12-65–12-67
DMA (continued)
functional description 12-48
global-control register 12-53
internal priority schemes for ’C32 12-62
interrupts 12-64
priorities 12-62
register 12-51
transfer-counter register 12-58
coprocessor, definition D-3
destination register 12-67–12-68
destination/source address regis-
ter 12-57–12-59
Initialization/reconfiguration 12-73
interrupt, CPU interaction 7-40
interrupt-enable register 12-59–12-62
interrupts 7-38
control bits 7-38
processing, block diagram 7-39, 7-40
memory transfer 12-67–12-68
single DMA timing 12-68
PRI and CPU/DMA arbitration rules for
’C32 12-64
registers, initialization 12-50
setup and use examples 12-74–12-80
source register 12-67–12-68
start 12-50
timing
expansion bus destination 12-72
on-chip destination 12-69
primary bus destination 12-70 12-71
transfer-counter register 12-58–12-59
word transfers 12-50
dual-access RAM, definition D-3
DX pins 12-22
E
event counters 12-2
example instruction 13-38–13-40
execute only 8-12
parallel store followed by single read 8-14
single store followed by two reads 8-13
expansion bus 9-2
control register 9-9–9-15
bits described 9-9
functional timing of operations 9-15
I/O cycles 9-21–9-36
interface, signals 9-5
programmable wait states 9-10–9-11,
10-15–10-16