Computer Hardware User's Guide

Index
Index-4
bitwise-logical
AND 13-62
3-operand 13-63
with complement (ANDN) 13-67
complement instruction (NOT) 13-184
OR instruction 13-188
block
diagram, TMS320C3x 1-3
repeat-mode
control bits 7-3
nested block repeats 7-8
operation 7-3–7-4
RC register value 7-7
registers (RC, RE, RS) 7-2
restrictions 7-6–7-7
RPTB instruction 7-4–7-5
RPTS instruction 7-5
size (BK) register 3-4
transfer completion 12-51
block-repeat (RS, RE) registers 3-17
boot loader
code description C-2
code listing C-4
definition D-2
flowchart C-3
hardware interface, TMS320C32 11-23
interrupt and trap vector mapping 11-11
memory 11-19
precautions 11-13
serial-port loading 11-11
TMS320C31 11-2–11-13
data stream 11-7
description 11-2
external memory loading 11-9
memory load flowchart 11-5
mode selection 11-2
mode selection flowchart 11-3
sequence 11-4
serial port load flowchart 11-6
TMS320C32 11-14–11-24
data stream 11-20
description 11-14
external memory interface 11-23
mode selection 11-14
mode selection flowchart 11-17
sequence 11-15
serial port load flowchart 11-18
branch
addressing modes 2-17
conditionally
delayed instruction (BcondD) 13-81
standard instruction (Bcond) 13-79
conflicts 8-4
delayed 7-9–7-10
execution 7-10
incorrect use of 7-9
incorrectly placed 7-7, 7-10
incorrectly placed 7-6
unconditionally
delayed instruction (BRD) 13-84
standard instruction (BR) 13-83
bus
cycles 10-39
IOSTRB 10-42
STRB0
10-39
STRB1
10-39
operation
external 2-19
internal 2-18
timing 10-39
buses
data 2-18
DMA 2-18
program 2-18
busy-waiting loop, example 7-16
byte-wide configured memory, TMS320C31 11-9
C
cache
control bits
cache clear bit (CC) 4-22
cache enable bit (CE) 4-22
cache freeze bit (CF) 4-22
hit 4-21
instruction 2-16, 4-19
algorithm 4-21–4-22
memory 2-13
architecture 4-19
miss 4-21
segment 4-21
subsegment 4-21
call, subroutine
conditionally instruction (CALLcond) 7-11,
13-86
instruction (CALL) 7-11, 13-85
response timing 7-12