Computer Hardware User's Guide

Glossary
D-5 Glossary
M
machine cycle: See CPU cycle .
mantissa: A component of a floating-point number consisting of a fraction
and a sign bit. The mantissa represents a normalized fraction whose
binary point is shifted by the exponent.
maskable interrupt: A hardware interrupt that can be enabled or disabled
through software.
memory-mapped register: One of the on-chip registers that point to ad-
dresses in memory. Some memory-mapped registers point to data
memory, and somepoint to input/output memory.
memory width: The number of bits that can be stored in a single external
memory address.
MFLOPS: Millions of floating point operations per second . A measure of
floating-point processor speed that counts of the number of floating-point
operations made per second. Also called megaflops.
microcomputer mode: A mode in which the on-chip ROM (boot loader) is
enabled. This mode is selected via the MP/MCBL pin.
microprocessor mode: A mode in which the on-chip ROM is disabled. This
mode is selected via the MP/MCBL pin. See also MP/MC pin.
MIPS: Million instructions per second.
miss: A condition in which, when the processor fetches an instruction, it is
not available in the cache.
MSB: Most significant bit. The highest-order bit in a word.
multiplier: A device that generates the product of two numbers.
N
NMI: Nonmaskable interrupt . A hardware interrupt that uses the same logic
as the maskable interrupts but cannot be masked.