Computer Hardware User's Guide

Glossary

D-4

IACK:

Interrupt acknowledge signal

. An output signal indicating that an in-

terrupt has been received and that the program counter is fetching the

interrupt vector that will force the processor into an interrupt service rou-

tine.

IE: See internal interrupt enable register.

I/O flag (IOF) register: Controls the function (general-purpose I/O or inter-

rupt) of the external pins. It also contains timer/DMA interrupt flags.

index registers: Two 32-bit registers (IR0 and IR1) that are used by the

ARAU for indexing an address.

internal interrupt: A hardware interrupt caused by an on-chip peripheral.

internal interrupt enable register: A register (in the CPU register file) that

determines whether the CPU or DMA responds to interrupts from exter-

nal interrupt pins, the serial ports, the timers, and the DMA coprocessor.

interrupt: A signal sent to the CPU that (when not masked) forces the CPU

into an ISR. This signal can be triggered by an external device, an on-

chip peripheral, or an instruction (TRAP, for example).

interrupt acknowledge (IACK): A signal indicating that an interrupt has

been received and that the program counter is fetching the interrupt vec-

tor location.

interrupt-trap table pointer (ITTP): A bit field in the status register that indi-

cates the starting location (base address) of the interrupt-trap vector

table. The base address is formed by left-shifting the value of the ITTP

bit field by 8 bits.

ISR:

Interrupt service routine

. A module of code that is executed in

response to a hardware or software interrupt.

ITTP: See

interrupt-trap table pointer

LSB:

Least significant bit.

The lowest-order bit in a word.