Computer Hardware User's Guide

TSTB3 Test Bit Fields, 3-Operand
13-248
Example 1 TSTB3 *AR5––(IR0),*+AR0(1)
Before Instruction After Instruction
AR0 80 992C AR0 80 992C
AR5 80 9885 AR5 80 9805
IR0 80 IR0 80
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 1
V 0 V 0
C 0 C 0
Data memory
809885h 898 809885h 898
80992Dh 767 80992Dh 767
2200 2200
1895 1895
Example 2 TSTB3 R4,*AR6––(IR0)
Before Instruction After Instruction
R4 00 0000 FBC4 R4 00 0000 FBC4
AR6 80 99F8 AR6 80 99F0
IR0 8 IR0 8
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8099F8h 1568 8099F8h 1568
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.