Computer Hardware User's Guide

Subtract Reverse Integer SUBRI
13-241 Assembly Language Instructions
Syntax SUBRI src, dst
Operation src – dst → dst
Operands src general addressing modes (G):
0 0 register (R
n , 0 ≤ n ≤ 27)
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst register (R n , 0 ≤ n ≤ 27)
Opcode
31 24 23 16 8 7 015
00 0 11 1
0 10
dst
G
src
Description The difference between the src operand and the dst operand is loaded into the
dst register. The dst and src operands are assumed to be signed integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C 1 if a borrow occurs; 0 otherwise
OVM Operation is affected by OVM bit value.
Example SUBRI *AR5++(IR0),R3
Before Instruction After Instruction
R3 00 0000 00DC R3 00 0000 014A
AR5 80 9900 AR5 80 9908
IR0 8 IR0 8
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809900h 226 809900h 226
550
330
550
220
Mode Bit