Computer Hardware User's Guide

SUBI3||STI Parallel SUBI3 and STI
13-238
Example SUBI3 R7,*+AR2(IR0),R1
|| STI R3,*++AR7
Before Instruction After Instruction
R1 00 0000 0000 R1 00 0000 00C8
R3 00 0000 0035 R3 00 0000 0035
R7 00 0000 0014 R7 00 0000 0014
AR2 80 982F AR2 80 982F
AR7 80 983B AR7 80 983C
IR0 10 IR0 10
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
80983Fh 0DC 80983Fh 0DC
80983Ch 0 80983Ch 35
53
200
53
220
20
20
220
53
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.