Computer Hardware User's Guide

Parallel SUBF3 and STF SUBF3||STF
13-233 Assembly Language Instructions
Example SUBF3 R1,*–AR4(IR1),R0
|| STF R7,*+AR5(IR0)
Before Instruction After Instruction
R0 00 0000 0000 R0 06 1B60 0000
R1 05 7B40 0000 R1 05 7B40 0000
R7 07 33C0 0000 R7 07 33C0 0000
AR4 80 98B8 AR4 80 98B8
AR5 80 9850 AR5 80 9850
IR0 10 IR0 10
IR1 8 IR1 8
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098B0h 70C8000 8098B0h 70C8000
809860h 0 809860h 733C000
7.768750e+01
1.4050e+02
1.4050e+02
1.79750e+02
1.79750e+02
6.28125e+01
1.79750e+02
6.28125e+01
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.