Computer Hardware User's Guide

SUBF3 Subtract Floating-Point Value, 3-Operand
13-230
Syntax SUBF3 src2, src1, dst
Operation src1 – src2 → dst
Operands src1 3-operand addressing modes (T):
0 0 register (R n 1, 0 ≤ n 1 ≤ 7)
0 1 indirect (
disp = 0, 1, IR0, IR1)
1 0 register (R n 1, 0 ≤ n 1 ≤ 7)
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 register (R n 2, 0 ≤ n 2 ≤ 7)
0 1 register (R n 2, 0 ≤ n 2 ≤ 7)
1 0 indirect (
disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst register (R n , 0 ≤ n ≤ 7)
Opcode
31 24 23 16 8 7 015
001 00 0
1 11
dst
T
src 1 src 2
Description The difference between the src1 and src2 operands is loaded into the dst reg-
ister. The src1 , src2 , and dst operands are assumed to be floating-point num-
bers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF 1 if a floating-point underflow occurs; unchanged otherwise
LV 1 if a floating-point overflow occurs; unchanged otherwise
UF 1 if a floating-point underflow occurs; 0 otherwise
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if a floating-point overflow occurs; 0 otherwise
C Unaffected
OVM Operation is not affected by OVM bit value.Mode Bit