Computer Hardware User's Guide

STI||STI Parallel STI and STI
13-222
Example STI R0,*++AR2(IR0)
|| STI R5,*AR0
Before Instruction After Instruction
R0 00 0000 00DC R0 00 0000 00DC
R5 00 0000 0035 R5 00 0000 0035
AR0 80 98D3 AR0 80 98D3
AR2 80 9830 AR2 80 9838
IR0 8 IR0 8
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809838h 0 809838h 0DC
8098D3h 0 8098D3h 35
53
220 220
53
53
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.