Computer Hardware User's Guide

Parallel Store Floating-Point Value STF||STF
13-217 Assembly Language Instructions
Syntax STF src2, dst2
|| STF src1 , dst1
Operation src2 → dst2
|| src1 → dst1
Operands src1 register (R n 1, 0 ≤ n 1 ≤ 7)
dst1 indirect ( disp = 0, 1, IR0, IR1)
src2 register (R n 2, 0 ≤ n 2 ≤ 7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
’C31 silicon revision 6.0 or greater
’C32 silicon revision 2.0 or greater
src1 register (R n 1, 0 ≤ n 1 ≤ 7)
dst1 indirect ( disp = 0, 1, IR0, IR1)
src2 register (R n 2, 0 ≤ n 2 ≤ 7)
dst2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
Opcode
31 24 23 16 8 7 015
11 000
00
00
src 1
0
dst 1
dst 2 src 2
Description Two STF instructions are executed in parallel. Both src1 and src2 are assumed
to be floating-point numbers.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.Mode Bit