Computer Hardware User's Guide

Parallel OR3 and STI OR3||STI
13-193 Assembly Language Instructions
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
Example OR3 *++AR2,R5,R2
|| STI R6,*AR1––
Before Instruction After Instruction
R2 00 0000 0000 R2 00 0080 9800
R5 00 0080 0000 R5 00 0080 0000
R6 00 0000 00DC R6 00 0000 00DC
AR1 80 9883 AR1 80 9882
AR2 80 9830 AR2 80 9831
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809831h 9800 809831h 9800
809883h 0 809883h 0DC
220
220220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.
Mode Bit