Computer Hardware User's Guide

Parallel NOT and STI NOT||STI
13-187 Assembly Language Instructions
Example NOT *+AR2,R3
|| STI R7,*––AR4 (IR1)
Before Instruction After Instruction
R3 00 0000 0000 R3 00 FFFF F3D0
R7 00 0000 00DC R7 00 0000 00DC
AR2 80 99CB AR2 80 99CB
AR4 80 9850 AR4 80 9840
IR1 10 IR1 10
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 1
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8099CCh 0C2F 8099CCh 0C2F
809840h 0 809840h 0DC
220
220
220
Note: Cycle Count
See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects
of operand ordering on the cycle count.