Computer Hardware User's Guide
NOT||STI
Parallel NOT and STI
13-186
Syntax NOT
src2, dst1
|| STI
src3, dst2
Operation ∼
src2
→
dst1
||
src3
→
dst2
Operands
src2
indirect (
disp
= 0, 1, IR0, IR1)
dst1
register (R
n
1, 0 ≤
n
1 ≤ 7)
src3
register (R
n
2, 0 ≤
n
2 ≤ 7)
dst2
indirect (
disp
= 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
’C31 silicon revision 6.0 or greater
’C32 silicon revision 2.0 or greater
src2
indirect (
disp
= 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n
1, 0 ≤
n
1 ≤ 7)
src3
register (R
n
2, 0 ≤
n
2 ≤ 7)
dst2
indirect (
disp
= 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 015
111001
dst
1
src
2
dst
21
src
3000
Description A bitwise-logical NOT and an integer store are performed in parallel. All regis-
ters are read at the beginning and loaded at the end of the execute cycle. This
means that if one of the parallel operations (STI) reads from a register and the
operation being performed in parallel (NOT) writes to the same register, STI
accepts the contents of the register as input before it is modified by the NOT.
If
src2
and
dst2
point to the same location,
src2
is read before the write to
dst2.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
Mode Bit