Computer Hardware User's Guide

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NOT

Bitwise-Logical Complement

13-184

Syntax NOT

src, dst

Operation ∼

src

→

dst

Operands

src

general addressing modes (G):

0 0 any CPU register

0 1 direct

1 0 indirect (disp = 0–255, IR0, IR1)

1 1 immediate

dst

any CPU register

Opcode

31 2423 16 8 7 015

000 01 1

0 11

dst src

Description The bitwise-logical complement of the

src

operand is loaded into the

dst

regis-

ter. The complement is formed by a logical NOT of each bit of the

src

operand.

The

dst

and

src

operands are assumed to be unsigned integers.

Cycles 1

Status Bits These condition flags are modified only if the destination register is R7–R0.

LUF Unaffected

LV Unaffected

UF 0

N MSB of the output

Z 1 if a 0 result is generated; 0 otherwise

V 0

C Unaffected

OVM Operation is affected by OVM bit value.

Mode Bit