Computer Hardware User's Guide

NEGI Negate Integer
13-178
Syntax NEGI src, dst
Operation 0 – src → dst
Operands src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 015
000 01 0
0 01
dst
G
src
Description The difference of the 0 and src operands is loaded into the dst register. The
dst and src operands are assumed to be signed integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C 1 if a borrow occurs; 0 otherwise
OVM Operation is affected by OVM bit value.
Example NEGI 174,R5 (174 = 0AEh)
Before Instruction After Instruction
R5 00 0000 00DC R5 00 FFFF FF52
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 1
Z 0 Z 0
V 0 V 0
C 0 C 1
–174
220
Mode Bit