Computer Hardware User's Guide

MPYI3||SUBI3 Parallel MPYI3 and SUBI3
13-172
or
MPYI3 *++AR0(1),R2,R0
|| SUBI3 *AR5
––(IR1),R4,R2
Before Instruction After Instruction
R0 00 0000 0000 R0 00 0000 1324
R2 00 0000 0032 R2 00 0000 0320
R4 00 0000 07D0 R4 00 0000 07D0
AR0 80 98E3 AR0 80 98E4
AR5 80 99FC AR5 80 99F0
IR1 0C IR1 0C
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098E4h 62 8098E4h 62
8099FCh 4B0 8099FCh 4B0
2000
4900
98
2000
50 800
1200
98
1200
Note: Cycle Count
One cycle if:
src3 and src4 are in internal memory
src3 is in internal memory and src4 is in external memory
Two cycles if:
src3 is in external memory and src4 is in internal memory
src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.