Computer Hardware User's Guide

MPYl3||ADDl3 Parallel MPYl3 and ADD13
13-166
Before Instruction After Instruction
R0 00 0000 0000 R0 00 0000 07D0
R3 00 0000 0000 R3 00 0000 0000
R4 00 0000 0064 R4 00 0000 0064
R7 00 0000 0014 R7 00 0000 0014
AR3 80 981F AR3 80 981F
AR5 80 996E AR5 80 996D
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
80981Eh 0FFFFFFCB 80981Eh 0FFFFFFCB
80996Eh 35 80996Eh 35
100
2000
–53
–53
100
53
20
20
53
Note: Cycle Count
One cycle if:
src3 and src4 are in internal memory
src3 is in internal memory and src4 is in external memory
Two cycles if:
src3 is in external memory and src4 is in internal memory
src3 and src4 are in external memory
For more information see Section 8.5, Clocking Memory Accesses, on page
8-24.