Computer Hardware User's Guide

Parallel MPYI3 and ADDI3 MPYI3||ADDI3
13-165 Assembly Language Instructions
Opcode
31 2423 16 8 7 015
10 001 0 P
src 4 src 3 src 1 src 2d1 d2
Description An integer multiplication and an integer addition are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
This means that if one of the parallel operations (MPYI3) reads from a register
and the operation being performed in parallel (ADDI3) writes to the same reg-
ister, MPYI3 accepts the contents of the register as input before it is modified
by the ADDI3.
Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as
register. The assignment of the source operands
srcA – srcD to the
src1 – src4 fields varies, depending on the combination of addressing modes
used, and the P field is encoded accordingly. To simplify processing when the
order is not significant, the assembler may change the order of operands in
commutative operations.
Cycles 1 (see Note: Cycle Count on page 13–167)
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 0
Z 0
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
OVM Operation is affected by OVM bit value.
Example MPYI3 R7,R4,R0
|| ADDI3 *–AR3,*AR5
––(1),R3
Mode Bit