Computer Hardware User's Guide

LSH3||STI Parallel LSH3 and STI
13-144
Example 2 LSH3 R7,*AR2––(1),R2
|| STI R0,*+AR0(1)
Before Instruction After Instruction
R0 00 0000 012C R0 00 0000 012C
R2 00 0000 0000 R2 00 0002 C000
R7 00 FFFF FFF4 R7 00 FFFF FFF4
AR0 80 98B7 AR0 80 98B7
AR2 80 9863 AR2 80 9862
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809863h 2C000000 809863h 2C000000
8098B8h 0 8098B8h 12C
300
300
–12 –12
300
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.