Computer Hardware User's Guide

LSH3||STI Parallel LSH3 and STI
13-142
Logical right shift:
0 → src2 → C
If the count operand is 0, no shift is performed, and the carry bit is set to 0.
The count operand is assumed to be a 7-bit signed integer, and the src2 and
dst1 operands are assumed to be unsigned integers. All registers are read at
the beginning and loaded at the end of the execute cycle. This means that
if one of the parallel operations (STI) reads from a register and the operation
being performed in parallel (LSH3) writes to the same register, STI accepts as
input the contents of the register before it is modified by the LSH3.
If
src2 and dst2 point to the same location, src2 is read before dst2 is written.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 output is generated; 0 otherwise
V 0
C Set to the value of the last bit shifted out; 0 for a shift count of 0
OVM Operation is affected by OVM bit value.Mode Bit