Computer Hardware User's Guide

LSH3 Logical Shift, 3-Operand
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Example 2 LSH3 *–AR4(IR1),R5,R3
Before Instruction After Instruction
R3 00 0000 0000 R3 00 0001 2C00
R5 00 12C0 0000 R5 00 12C0 0000
AR4 80 9908 AR4 80 9908
IR1 4 IR1 4
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809904h 0FFFFFFF4 809904h 0FFFFFFF4
–12
–12
Note: Cycle Count
See Section 8.5.2,
Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.