Computer Hardware User's Guide

LDI||STI Parallel LDI and STI
13-132
Example LDI *–AR1(1),R2
|| STI R7,*AR5++(IR0)
Before Instruction After Instruction
R2 00 0000 0000 R2 00 0000 00DC
R7 00 0000 0035 R7 00 0000 0035
AR1 80 98E7 AR1 80 98E7
AR5 80 982C AR5 80 9834
IR0 8 IR0 8
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098E6h 0DC 8098E6h 0DC
80982Ch 0 80982Ch 35
220
53
220
53
220
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.