Computer Hardware User's Guide

Parallel LDI and STI LDI||STI
13-131 Assembly Language Instructions
Syntax LDI src2, dst1
|| STI src3, dst2
Operation src2 → dst1
|| src3 → dst2
Operands src2 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0 ≤ n 1 ≤ 7)
src3 register (R n 2, 0 ≤ n 2 ≤ 7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented on the following devices:
’C31 silicon revision 6.0 or greater
’C32 silicon revision 2.0 or greater
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst1 register (R n 1, 0 ≤ n 1 ≤ 7)
src3 register (R n 2, 0 ≤ n 2 ≤ 7)
dst2 indirect ( disp = 0, 1, IR0, IR1)
Opcode
31 2423 16 8 7 015
110110
dst 1 src 2 dst 21 000 src 3
Description An integer load and an integer store are performed in parallel. If src2 and dst2
point to the same location, src2 is read before the dst2 is written.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.
Mode Bit