Computer Hardware User's Guide

Parallel LDF and LDF LDF||LDF
13-119 Assembly Language Instructions
Syntax LDF src2, dst2
|| LDF src1, dst1
Operation src2 → dst2
|| src1 → dst1
Operands src1 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0 ≤ n 1 ≤ 7)
src2 indirect ( disp = 0, 1, IR0, IR1)
dst2 register (R n 2, 0 ≤ n 2 ≤ 7)
This instruction’s operands have been augmented on the following devices:
’C31 silicon revision 6.0 or greater
’C32 silicon revision 2.0 or greater
src1 indirect ( disp = 0, 1, IR0, IR1)
dst1 register (R n 1, 0 ≤ n 1 ≤ 7)
src2 indirect ( disp = 0, 1, IR0, IR1) or any CPU register
dst2 register (R n 2, 0 ≤ n 2 ≤ 7)
Opcode
31 2423 16 8 7 015
110001
dst 2 src 2 src 10 dst 1000
Description Two floating-point loads are performed in parallel. If the LDFs load the same
register, the assembler issues a warning. The result is that of LDF src2, dst2.
Cycles 1
Status Bits LUF Unaffected
LV Unaffected
UF Unaffected
N Unaffected
Z Unaffected
V Unaffected
C Unaffected
OVM Operation is not affected by OVM bit value.Mode Bit