Computer Hardware User's Guide

ASH3||STI Parallel ASH3 and STI
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Example ASH3 R1,*AR6++(IR1),R0
|| STI R5,*AR2
Before Instruction After Instruction
R0 00 0000 0000 R0 00 FFFF FFAE
R1 00 0000 FFE8 R1 00 0000 FFE8
R5 00 0000 0035 R5 00 0000 0035
AR2 80 98A2 AR2 80 98A2
AR6 80 9900 AR6 80 998C
IR1 8C IR1 8C
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
809900h 0AE000000 809900h 0AE000000
8098A2h 0 8098A2h 35
–24
–24
53
53
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.