Computer Hardware User's Guide

Bitwise-Logical ANDN, 3-Operand ANDN3
13-69 Assembly Language Instructions
Syntax ANDN3 src2, src1, dst
Operation src1 AND ∼ src2 → dst
Operands src1 3-operand addressing modes (T):
0 0 any CPU register
0 1 indirect (
disp = 0, 1, IR0, IR1)
1 0 any CPU register
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 any CPU register
0 1 any CPU register
1 0 indirect (
disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IO0, IR1)
dst register (R n , 0 ≤ n ≤ 27)
Opcode
31 24 23 16 8 7 015
0010001
dst src 100
T
src 2
Description The bitwise-logical AND between the src1 operand and the bitwise-logical
complement (∼) of the src2 operand is loaded into the dst register. The src1 ,
src2 , and dst operands are assumed to be unsigned integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.Mode Bit