Computer Hardware User's Guide

Bitwise-Logical AND With Complement ANDN
13-67 Assembly Language Instructions
Syntax ANDN src , dst
Operation dst AND ∼ src → dst
Operands src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate (not sign extended)
dst any CPU register
Opcode
31 24 23 16 8 7 015
0000001
dst src 10
G
Description The bitwise-logical AND between the dst operand and the bitwise-logical com-
plement (∼) of the src operand is loaded into the dst register. The dst and src
operands are assumed to be unsigned integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a 0 result is generated; 0 otherwise
V 0
C Unaffected
OVM Operation is not affected by OVM bit value.
Mode Bit