Computer Hardware User's Guide

AND3||STI Parallel AND3 and STI
13-66
OVM Operation is not affected by OVM bit value.
Example AND3 *+AR1(IR0),R4,R7
|| STI R3,*AR2
Before Instruction After Instruction
R0 00 0000 0008 R0 00 0000 0008
R3 00 0000 0035 R3 00 0000 0035
R4 00 0000 A323 R4 00 0000 A323
R7 00 0000 0000 R7 00 0000 0003
AR1 80 99F1 AR1 80 99F1
AR2 80 983F AR2 80 983F
LUF 0 LUF 0
LV 0 LV 0
UF 0 UF 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8099F9h 5C53 8099F9h 5C53
80983Fh 0 80983Fh 35
53
53
53
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit