Computer Hardware User's Guide

Parallel ADDl3 and STI ADDl3||STI
13-61 Assembly Language Instructions
OVM Operation is affected by OVM bit value.
Example ADDI3 *AR0
––(IR0),R5,R0
 STI R3,*AR7
Before Instruction After Instruction
R0 00 0000 0000 R0 00 0000 0208
R3 00 0000 0035 R3 00 0000 0035
R5 00 0000 00DC R5 00 0000 00DC
AR0 80 992C AR0 80 9920
AR7 80 983B AR7 80 983B
IR0 OC IR0 OC
LUF 0 LUF 0
LV 0 LV 0
UF 0 UV 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
80992C 12C 80992C 12C
80983B 0 80983B 35
53
300
300
53
220
220
53
520
Note: Cycle Count
See Section 8.5.2,
Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit