Computer Hardware User's Guide

ADDF3||STF Parallel ADDF3 and STF
13-56
OVM Operation is not affected by OVM bit value.
Example ADDF3 *+AR3(IR1),R2,R5
|| STF R4,*AR2
Before Instruction After Instruction
R2 07 0C80 0000 R2 07 0C80 0000
R4 05 7B40 0000 R4 05 7B40 0000
R5 00 0000 0000 R5 08 2020 0000
AR2 80 98F3 AR2 80 98F3
AR3 80 9800 AR3 80 9800
IR1 0A5 IR1 0A5
LUF 0 LUF 0
LV 0 LV 0
UF 0 UV 0
N 0 N 0
Z 0 Z 0
V 0 V 0
C 0 C 0
Data memory
8098A5h 733C000 8098A5h 733C000
8098F3h 0 8098F3h 57B4000
1.4050e+02
6.281250e+01
1.79750e+02
1.4050e+02
6.281250e+01
3.20250e+02
1.79750e+02
6.28125e+01
Note: Cycle Count
See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of
operand ordering on the cycle count.
Mode Bit