Computer Hardware User's Guide

Memory Organization
2-15 Architectural Overview
Figure 2–6. Memory Organization of the TMS320C31
RDY
HOLD
HOLDA
STRB
R/W
D31–D0
A23–A0
DMAADDR bus
DMADATA bus
DADDR2 bus
DADDR1 bus
DDATA bus
PADDR bus
PDATA bus
Program counter/
instruction register
CPU
DMA
controller
32 24 24 32 24 24 32
32 24 32 24 24 32 24
32
Peripheral bus
Multiplexer
Multiplexer
Cache
(64 32)
RAM
block 0
(1K 32)
RAM
block 1
(1K 32)
Boot ROM