Computer Hardware User's Guide

Add Integer With Carry, 3-Operand ADDC3
13-49 Assembly Language Instructions
Syntax ADDC3 src2 , src1 , dst
Operation src1 + src2 + C → dst
Operands src1 3-operand addressing modes (T):
0 0 any CPU register
0 1 indirect (
disp = 0, 1, IR0, IR1)
1 0 any CPU register
1 1 indirect ( disp = 0, 1, IR0, IR1)
src2 3-operand addressing modes (T):
0 0 any CPU register
0 1 any CPU register
1 0 indirect (
disp = 0, 1, IR0, IR1)
1 1 indirect ( disp = 0, 1, IR0, IR1)
dst any CPU register
Opcode
31 2423 16 8 7 015
00100 0 T
src 10
dst
0 src 20
Description The sum of the src1 and src2 operands and the carry (C) flag is loaded into
the dst register. The src1 , src2 , and dst operands are assumed to be signed
integers.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
U 0
N 1 if a negative result is generated; 0 otherwise
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C 1 if a carry occurs; 0 otherwise
OVM Operation is affected by OVM bit value.Mode Bit