Computer Hardware User's Guide
ABSI||STI
Parallel ABSI and STI
13-46
Syntax ABSI
src2
,
dst1
|| STI
src3, dst2
Operation |
src2
| →
dst1
||
src3
→
dst2
Operands
src2
indirect (
disp
= 0, 1, IR0, IR1)
dst1
register (R
n
1, 0 ≤ 1 ≤ 7)
src3
register (R
n
2, 0 ≤
n
2 ≤ 7)
dst2
indirect (
disp
= 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
’C31 silicon revision 6.0 or greater
’C32 silicon revision 2.0 or greater
src2
indirect (
disp
= 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n
1, 0 ≤
n
1 ≤ 7)
src3
register (R
n
2, 0 ≤
n
2 ≤ 7)
dst2
indirect (
disp
= 0, 1, IR0, IR1)
Opcode
31 24 23 16 8 7 015
110010
dst
1
src
2
dst
21
src
3
000
Description An integer absolute value and an integer store are performed in parallel. All
registers are read at the beginning and loaded at the end of the execute cycle.
If one of the parallel operations (STI) reads from a register and the operation
being performed in parallel (ABSI) writes to the same register, STI accepts the
contents of the register as input before it is modified by the ABSI.
If
src2
and
dst2
point to the same location,
src2
is read before the write to
dst2.
An overflow occurs if
src
= 80000000h. If ST(OVM) = 1, the result is
dst
=
7FFFFFFFh. If ST(OVM) = 0, the result is
dst
= 80000000h.
Cycles 1