Computer Hardware User's Guide

ABSI Absolute Value of Integer
13-44
Syntax ABSI src , dst
Operation | src | → dst
Operands src general addressing modes (G):
0 0 any CPU register
0 1 direct
1 0 indirect (disp = 0–255, IR0, IR1)
1 1 immediate
dst any CPU register
Opcode
31 24 23 16 8 7 015
00000 0
src 0
dst
G10
Description The absolute value of the src operand is loaded into the dst register. The src
and dst operands are assumed to be signed integers.
An overflow occurs if src = 80000000h. If ST(OVM) = 1, the result is
dst = 7FFFFFFFh. If ST(OVM) = 0, the result is dst = 80000000h.
Cycles 1
Status Bits These condition flags are modified only if the destination register is R7–R0.
LUF Unaffected
LV 1 if an integer overflow occurs; unchanged otherwise
UF 0
N 0
Z 1 if a 0 result is generated; 0 otherwise
V 1 if an integer overflow occurs; 0 otherwise
C Unaffected
Mode Bit OVM Operation is affected by OVM bit value.