Computer Hardware User's Guide

Group Addressing Mode Instruction Encoding
13-20
13.4 Group Addressing Mode Instruction Encoding
The six addressing types (covered in Section 6.1, Addressing Types , on
page 6-2) form these four groups of addressing modes:
General addressing modes (G)
3-operand addressing modes (T)
Parallel addressing modes (P)
Conditional-branch addressing modes (B)
13.4.1 General Addressing Modes
Instructions that use the general addressing modes are general-purpose
instructions, such as ADDI, MPYF, and LSH. Such instructions usually have
this form:
dst operation src → dst
In the syntax, the destination operand is signified by dst and the source operand
by src ; operation defines an operation to be performed on the operands using the
general addressing modes. Bits 31–29 are 0, indicating general addressing
mode instructions. Bits 22 and 21 specify the general addressing mode (G) field,
which defines how bits 15–0 are to be interpreted for addressing the
src operand.
Options for bits 22 and 21 (G field) are as follows:
G Mode
00 Register (all CPU registers unless specified otherwise)
0 1 Direct
1 0 Indirect
11
Immediate
If the src and dst fields contain register specifications, the value in these
fields contains the CPU register addresses as defined by Table 13–10. For
the general addressing modes, the following values of AR n are valid:
AR n , 0 ≤ n ≤ 7