Computer Hardware User's Guide

Parallel Instruction Set Summary
13-17 Assembly Language Instructions
13.3 Parallel Instruction Set Summary
Table 13–9 lists the ’C3x instruction set in alphabetical order. Each table
entry shows the instruction mnemonic, description, and operation. Refer to
Section 13.1 for a functional listing of the instructions and individual instruc-
tion descriptions.
Table 13–9. Parallel Instruction Set Summary
(a) Parallel arithmetic with store instructions
Mnemonic Description Operation
ABSF
|| STF
Absolute value of a floating point | src 2| → dst 1
||
src 3 → dst 2
ABSI
|| STI
Absolute value of an integer | src 2| → dst 1
||
src 3 → dst 2
ADDF3
|| STF
Add floating-point value src 1 + src 2 → dst 1
||
src 3 → dst 2
ADDI3
|| STI
Add integer src 1 + src 2 → dst 1
||
src 3 → dst 2
AND3
|| STI
Bitwise-logical AND
src 1 AND src 2 → dst 1
||
src 3 → dst 2
ASH3
|| STI
Arithmetic shift If
count ≥ 0:
(
src 2 << count ) → dst 1
||
src 3 → dst 2
Else:
(
src 2 >> | count |) → dst 1
||
src 3 → dst 2
FIX
|| STI
Convert floating-point value to integer Fix (
src 2) → dst 1
||
src 3 → dst 2
FLOAT
|| STF
Convert integer to floating-point value Float( src 2) → dst 1
||
src 3 → dst 2
Legend: count register addr (R7–R0) op3 register addr (R0 or R1)
dst 1 register addr (R7–R0) op6 register addr (R2 or R3)
dst 2 indirect addr ( disp = 0, 1, IR0, IR1) src 1 register addr (R7–R0)
op1, op2, op4, and op5
src 2 indirect addr ( disp = 0, 1, IR0, IR1)
Any two of these operands must be
src 3 register addr (R7–R0)
specified using register addr; the remaining
two must be specified using indirect.