Computer Hardware User's Guide

ManualsBrandsTexas Instruments ManualsNetwork CardTMS320C3x

471

472

473

474

475

476

477

478

479

480

Instruction Set Summary

13-13

Assembly Language Instructions

Table 13–8. Instruction Set Summary (Continued)

Mnemonic OperationDescription

LDI

cond

Load integer conditionally If

cond

= true,

src

→ Dreg

Else, Dreg is not changed

LDII Load integer, interlocked Signal interlocked operation

src

→ Dreg

LDM Load floating-point mantissa

src

(mantissa) → R

(mantissa)

LDP Load data page pointer

src

→ data page pointer

LOPOWER Divide clock by 16 H1/16

→ H1

LSH Logical shift If

count

≥ 0:

(Dreg left-shifted by

count

) → Dreg

Else:

(Dreg right-shifted by |

count

|) → Dreg

LSH3 Logical shift (3-operand) If

count

≥ 0:

(

src

left-shifted by

count

) → Dreg

Else:

(

src

right-shifted by |

count

|) → Dreg

MAXSPEED Restore clock to regular speed H1/16

→ H1

MPYF Multiply floating-point values

src

× R

→ R

MPYF3 Multiply floating-point value (3-operand)

src

1 ×

src

2 → R

MPYI Multiply integers

src

× Dreg → Dreg

MPYI3 Multiply integers (3-operand)

src

1 ×

src

2 → Dreg

NEGB Negate integer with borrow 0 –

src

– C → Dreg

NEGF Negate floating-point value 0 –

src

→ R

NEGI Negate integer 0 –

src

→ Dreg

Legend: AR

auxiliary register

(AR7–AR0) RE repeat interrupt register

C carry bit RM repeat mode bit

src

conditional-branch addressing modes R

count

shift value (general addressing modes) RS repeat start register

cond

condition code SP stack pointer

Daddr destination memory address Sreg register address (any register)

Dreg register address (any register) ST status register

GIE global interrupt enable register

src

general addressing modes

N any trap vector 0–27

src

1 3-operand addressing modes

PC program counter

src

2 3-operand addressing modes

RC repeat counter register TOS top of stack