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Instruction Set Summary

13-12

Table 13–8. Instruction Set Summary (Continued)

Mnemonic OperationDescription

cond

Decrement and branch conditionally

(standard)

– 1 → AR

cond

= true and AR

≥ 0:

If C

src

is a register, C

src

→ PC

If C

src

is a value, C

src

+ PC + 1 → PC

Else, PC + 1

→ PC

cond

D Decrement and branch conditionally

(delayed)

– 1 → AR

cond

= true and AR

≥ 0:

If C

src

is a register, C

src

→ PC

If C

src

is a value, C

src

+ PC + 3 → PC

Else, PC + 1

→ PC

FIX Convert floating-point value to integer Fix (

src

) → Dreg

FLOAT Convert integer to floating-point value Float(

src

) → R

IACK Interrupt acknowledge Dummy read of

src

IACK toggled low, then high

IDLE Idle until interrupt PC + 1

→ PC

Idle until next interrupt

IDLE2 Low-power idle Idle until next interrupt stopping internal clocks

LDE Load floating-point exponent

src

(exponent) → R

(exponent)

LDF Load floating-point value

src

→ R

LDF

cond

Load floating-point value conditionally If

cond

= true,

src

→ R

Else, R

is not changed

LDFI Load floating-point value, interlocked Signal interlocked operation

src

→ R

LDI Load integer

src

→ Dreg

Legend: AR

auxiliary register

(AR7–AR0) RE repeat interrupt register

C carry bit RM repeat mode bit

src

conditional-branch addressing modes R

count

shift value (general addressing modes) RS repeat start register

cond

condition code SP stack pointer

Daddr destination memory address Sreg register address (any register)

Dreg register address (any register) ST status register

GIE global interrupt enable register

src

general addressing modes

N any trap vector 0–27

src

1 3-operand addressing modes

PC program counter

src

2 3-operand addressing modes

RC repeat counter register TOS top of stack