Computer Hardware User's Guide

DMA Controller
12-72
Figure 12–49. DMA Timing When Destination is an IOSTRB Bus
Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source on chip R
1
R
2
R
3
R
4
R
5
Destination IOSTRB
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
W
3
W
3
W
3
W
3
W
4
W
4
W
4
W
4
1+(2+C
w
) T
Destination
IOSTRB
C
w
C
w
C
w
C
w
1
+
(2
+
C
w
)
T
(’C30 only)
Source STRB bus
R
1
R
1
R
1
I R
2
R
2
R
2
I R
3
R
3
R
3
I
C
r
C
r
C
r
(2 + C
r
+ 2 + C
w
) + (2 +
C
w
+
max (1, C
r
–
C
w
+ 1)) (
T
–
1)
Destination IOSTRB bus
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
W
3
W
3
W
3
W
3
max
(1
,
C
r
–
C
w
+
1))
( T
–
1)
Destination
IOSTRB
bus
C
w
C
w
C
w
Source STRB0, STRB1,
MSTRB bus
R
1
R
1
R
1
I R
2
R
2
R
2
I
C
r
C
r
(2 C 2 C ) T ( T 1)
Destination IOSTRB W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
(2
+
C
r
+
2
+
C
w
)
T
+
( T
–
1)
C
w
C
w
Legend:
T = Number of transfers W = Single-cycle writes
Cr = Source-read wait states R
n
= Multicycle reads
Cw = Destination-write wait states W
n
= Multicycle writes
R = Single-cycle reads I = Internal register cycle
†
Write followed by read incurs in one extra cycle.