Computer Hardware User's Guide

DMA Controller
12-71
Peripherals
Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued)
Cycles
(H1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source
IOSTRB
R
1
R
1
R
1
R
1
I R
2
R
2
R
2
R
2
I
†
IOSTRB
bus
C
w
C
w
†
Destination
STRB0,
STRB1, or
MSTRB
bus
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
(3 + C
r
+ 2 + C
w
) T + 0.5 (T – 1)
†
C
w
C
w
(’C30 only)
Source
STRB bus
R
1
R
1
R
1
I R
2
R
2
R
2
I R
3
R
3
R
3
I
C
r
C
r
C
r
(2 + C
r
+ 2 + C
w
) + (2 + C
w
+ max[1, C
r
– C
w
+ 1])
Destination
MSTRB
bus
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
W
3
W
3
W
3
W
3
(T–1)
C
w
C
w
C
w
Legend:
T = Number of transfers W = Single-cycle writes
C
r
= Source-read wait states R
n
= Multicycle reads
C
w
= Destination-write wait states W
n
= Multicycle writes
R = Single-cycle reads I = Internal register cycle
†
Write followed by read incurs in one extra half-cycle.