Computer Hardware User's Guide
DMA Controller
12-70
Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus
Cycles
(H1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Rate
Source
on chip
R
1
R
2
R
3
R
4
R
5
Destination
STRB,
STRB0,
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
W
3
W
3
W
3
W
3
W
4
W
4
W
4
W
4
. . .
(1 + 2 +
C
w
)
T
STRB1,
MSTRB
bus
C
w
C
w
C
w
C
w
Source
STRB,
STRB0
R
1
R
1
R
1
I R
2
R
2
R
2
I
STRB0
,
STRB1
bus
C
r
C
r
(2 +
C
r
+ 2 +
C
w
)
T
+ 0.5 (
T
– 1)
Destination
STRB
,
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
. . .
STRB
,
STRB0,
STRB1
bus
C
w
C
w
(3.5 +
C
r + 2 +
C
w)
T
+ .5 (
T
– 1)
(’C30 only)
Source
R
1
R
1
R
1
R
1
I R
2
R
2
R
2
R
2
I R
3
R
3
R
3
R
3
I R
4
R
4
R
4
R
4
Source
IOSTRB
C
r
C
r
C
r
C
r
(3 + C
r
+ 2 + C
w
) + (2 + C
w
+ max[1, C
r
– C
w
+ 1])
(
T
–
1)
Destination
W
1
W
1
W
1
W
1
W
2
W
2
W
2
W
2
W
3
W
3
W
3
W
3
(
T
–1)
STRB bus
C
w
C
w
C
w
Legend:
T = Number of transfers W = Single-cycle writes
C
r
= Source-read wait states R
n
= Multicycle reads
C
w
= Destination-write wait states W
n
= Multicycle writes
R = Single-cycle reads I = Internal register cycle
†
Write followed by read incurs in one extra half-cycle.