Computer Hardware User's Guide
DMA Controller
12-69
Peripherals
Figure 12–47. DMA Timing When Destination is On Chip
Cycles (H1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Rate
Source on chip
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
(1+1)
T
Destination on chip
W
1
W
2
W
3
W
4
W
5
W
6
W
7
(1
+
1)
T
Source STRB STRB0 STRB1 MSTRB bus
R
1
R
1
R
1
I R
2
R
2
R
2
I R
3
R
3
R
3
I
Source
STRB
,
STRB0
,
STRB1
,
MSTRB
bus
C
r
C
r
C
r
(2 +
C
r
+1)
T
Destination on chip
W
1
W
2
W
3
Source IOSTRB bus
R
1
R
1
R
1
R
1
I R
2
R
2
R
2
R
2
I R
3
R
3
R
3
R
3
I
Source
IOSTRB
bus
C
r
C
r
C
r
(3 +
C
r
+ 1)
T
Destination on chip
W
1
W
2
W
3
Legend:
T = Number of transfers W = Single-cycle writes
C
r
= Source-read wait states R
n
= Multicycle reads
C
w
= Destination-write wait states W
n
= Multicycle writes
R = Single-cycle reads I = Internal register cycle