Computer Hardware User's Guide

DMA Controller
12-60
Figure 12–41. TMS320C30 and TMS320C31 CPU/DMA
Interrupt-Enable Register
xx
EDINT ETINT1 ETINT0 ERINT1 EXINT1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
xxxxxxxx
ERINT0 EXINT0 EINT3 EINT2 EINT1 EINT0
(DMA) (DMA) (DMA)(DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) (DMA)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
xx
EDINT ETINT1 ETINT0 ERINT1 EXINT1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xxxxxxxx
ERINT0 EXINT0 EINT3 EINT2 EINT1 EINT0
(CPU) (CPU) (CPU)(CPU) (CPU) (CPU) (CPU) (CPU) (CPU) (CPU) (CPU)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Notes: 1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12–42. TMS320C32 CPU/DMA Interrupt-Enable Register
EDINT1
(CPU)
xxxx
ETINT0
(CPU)
ETINT1
(CPU)
EDINT0
(CPU)
EINT0
(CPU)
EINT3
(DMA1)
ETINT1
(DMA1)
EXINT0
(DMA0)
EINT1
(DMA0)
EINT2
(DMA1)
ETINT1
(DMA0)
EDINT1
(DMA0)
ETINT0
(DMA1)
ERINT0
(DMA1)
EINT3
(DMA0)
EINT2
(DMA0)
EINT0
(DMA0)
EINT1
(DMA1)
EINT0
(DMA1)
EDINT0
(DMA1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
xx
xx
R/W R/W
R/W
R/W
R/W R/W R/W R/W R/W R/W
ETINT0
(DMA0)
R/WR/WR/WR/WR/W
EINT1
(CPU)
EINT2
(CPU)
EINT3
(CPU)
EXINT0
(CPU)
xx
xx
ERINT0
(CPU)
Notes: 1) R = read, W = write
2) xx = reserved bit, read as 0