Computer Hardware User's Guide

DMA Controller
12-52
At reset, each DMA-channel control register is set to 0. This makes the DMA
channels lower-priority than the CPU, sets up the source address and destination
address to be calculated through linear addressing, and configures the DMA
channel in the unified mode.
Figure 12–35. Memory-Mapped Locations for DMA Channels
Address Register
808000h
DMA 0 global control
808004h DMA 0 source address
808006h DMA 0 destination address
808008h DMA 0 transfer counter
808010h DMA 1 global control
†
808014h DMA 1 source address
†
808016h DMA 1 destination address
†
808018h DMA 1 transfer counter
†
†
’C32 only